`timescale 1ns / 1ps
module a4_sim;
    reg        cin;
    reg  [3:0] a;
    reg  [3:0] b;
    wire       cout;
    wire [3:0] sum;
    a4 uut(cin, a, b, cout, sum);
    initial begin
         cin = 0; a = 4'b0000; b = 4'b0000;
        #20  cin = 1; a = 4'b0101; b = 4'b0110;
        #20  cin = 0; a = 4'b1111; b = 4'b0001;
    end
endmodule